GitHub

VirTex: Learning Visual Representations from Textual Annotations

VirTex is a pretraining approach which uses semantically dense captions to learn visual representations. We train CNN + Transformers from scratch on COCO Captions, and transfer the CNN to downstream ...
GitHub

PicoRV32 - A Size-Optimized RISC-V CPU

PicoRV32 is a CPU core that implements the RISC-V RV32IMC Instruction Set. It can be configured as RV32E, RV32I, RV32IC, RV32IM, or RV32IMC core, and optionally contains a built-in interrupt ...
IEEE

Design Techniques for Xilinx Virtex FPGA Configuration Memory Scrubbers

Abstract: SRAM-based FPGAs are in-field reconfigurable an unlimited number of times. This characteristic, together with their high performance and high logic density, proves to be very convenient for ...
IEEE

The Design of a 16-Channel 15 ps TDC Implemented in a 65 nm FPGA

Abstract: We present the implementation of a high-resolution Time-to-Digital Converter (TDC) in a Field Programmable Gate Array (FPGA) from Xilinx Virtex-5 family. The design of the TDC is based on a ...