Opinion

The 3D-Flow Architecture Breakthrough: A Universal, Scalable Digital Processor for Real-Time Pattern Recognition in High-Rate Data Streams -- A Platform to Save Millions of ...

Public records clearly shows that for the past 25 years, CERN has repeatedly built inadequate FPGA-based Level-1 Triggers, necessitating multiple rebuilds. During the Higgs boson discovery ...
IEEE

Design Techniques for Xilinx Virtex FPGA Configuration Memory Scrubbers

Abstract: SRAM-based FPGAs are in-field reconfigurable an unlimited number of times. This characteristic, together with their high performance and high logic density, proves to be very convenient for ...
IEEE

Comparison of Xilinx Virtex-II FPGA SEE sensitivities to protons and heavy ions

Abstract: A comparison of heavy-ion and proton-induced single event effect sensitivities has been made using the Xilinx Virtex-II field programmable gate array (FPGA). Recently fabricated test samples ...
GitHub

PicoRV32 - A Size-Optimized RISC-V CPU

PicoRV32 is a CPU core that implements the RISC-V RV32IMC Instruction Set. It can be configured as RV32E, RV32I, RV32IC, RV32IM, or RV32IMC core, and optionally contains a built-in interrupt ...
GitHub

VirTex: Learning Visual Representations from Textual Annotations

VirTex is a pretraining approach which uses semantically dense captions to learn visual representations. We train CNN + Transformers from scratch on COCO Captions, and transfer the CNN to downstream ...
Microsoft

Ken Eguro

Ken joined the Embedded and Reconfigurable Computing Group in 2008 and is an Affiliate Assistant Professor in the Electrical Engineering Department at the University of Washington (opens in new tab).