IEEE

Large Language Model for Verilog Generation with Code-Structure-Guided Reinforcement Learning

Abstract: Recent advancements in large language models (LLMs) have sparked significant interest in the automatic generation of Register Transfer Level (RTL) designs, particularly using Verilog.
IEEE

GEMMV: An LLM-Based Automated Performance-Aware Framework for GEMM Verilog Generation

Abstract: Recent advancements in artificial intelligence (AI) models have intensified the need for specialized AI accelerators. The design of optimized general matrix multiplication (GEMM) module ...
GitHub

datapath-design

Greatest Common Divisor calculator showcasing CPU-like controller + datapath architecture using subtraction-based Euclidean algorithm. Demonstrates synthesizable FSM design vs behavioral modeling ...