IEEE

Design of Adder Circuits using GNRFETs in Ternary Logic

Abstract: This paper presents the design of ternary adder schematics with graphene nanoribbon field effect transistor (GNRFET). The adder circuits are developed by using the basic, universal and ...
IEEE

FPGA Design and Implementation of BCH Encoders and Decoders Using Pipelined Architecture for High Throughput Applications

This paper presents the design and FPGA implementation of a high-throughput BCH (n,k) encoder and decoder using a fully pipelined architecture. Unlike conventional designs based on finite state ...