EDN

SpringSoft turns the power of Verdi on SystemVerilog test benches

SystemVerilog was supposed to be such a boon to verification engineers. By providing a Verilog-like language with extensions that made it easy to write transactors, assertions, and checkers, the ...
Design-Reuse

Using Tcl to create a virtual component in Verilog

It has long been a goal to put realistic prototypes or models into system developer's hands as soon as possible. This has been accomplished with FPGAs, C language models and sometimes co-simulation ...
Electronic Design

Development Environment Supports Mixed C++ And HDL Test Benches

TestBencher Pro v8.0 adds support for mixed C++ and hardware description language (HDL) test benches using the open standard TestBuilder library. This library offers useful verification capabilities, ...
EDN

Spotty support stymies broader acceptance of System Verilog, users say

SAN FRANCISCO — A handful of chip and systems companies said they are seeing real benefits from experiments and limited adoption of System Verilog, mainly in back-end design areas such as verification ...
Electronic Design

The MathWorks App Generates HDL Code From System Models

The Simulink HDL Coder automatically generates synthesizable hardware description language (HDL) code from models created in the company’s Simulink and Stateflow software. It produces ...
Semiconductor Engineering

Things You Never Knew About System Verilog

System Verilog is considered the current standard for a combined hardware description and verification language, and has been welcomed with open arms since it was approved by IEEE in 2005. Its ...
Semiconductor Engineering

Quality time?

System-Level Design sat down to discuss the future of verification with Olivier Haller, design verification team leader for STMicroelectronics’ functional verification group; Hillel Miller, functional ...