Google introduces TurboQuant, cutting LLM memory usage by 6x with no accuracy loss

The biggest memory burden for LLMs is the key-value cache, which stores conversational context as users interact with AI ...
WinBuzzer

Google’s TurboQuant Algorithm Slashes LLM Memory Use by 6x

Google has published TurboQuant, a KV cache compression algorithm that cuts LLM memory usage by 6x with zero accuracy loss, ...

Nvidia says it can shrink LLM memory 20x without changing model weights

Nvidia's KV Cache Transform Coding (KVTC) compresses LLM key-value cache by 20x without model changes, cutting GPU memory ...
TechSpot

AMD 3D V-Cache CPU memory used to create incredibly fast RAM disk

Why it matters: A RAM drive is traditionally conceived as a block of volatile memory "formatted" to be used as a secondary storage disk drive. RAM disks are extremely fast compared to HDDs or even ...
VentureBeat

AMD stacks memory cache in 3D to boost datacenter CPUs

Join our daily and weekly newsletters for the latest updates and exclusive content on industry-leading AI coverage. Learn More Advanced Micro Devices is announcing it is shipping its third-generation ...
EDN

MRAM technologies: from space applications to unified cache memory?

Magneto-resistive random access memory (MRAM) is a non-volatile memory technology that relies on the (relative) magnetization state of two ferromagnetic layers to store binary information. Throughout ...
NextBigFuture

Tesla Not Compute Limited for FSD AI Means 100+ Exaflops and 1+ Exabyte of Cache Memory

Tesla indicated in August, 2023 they were activating 10,000 Nvidia H100 cluster and over 200 Petabytes of hot cache (NVMe) storage. This memory is used to train the FSD AI on the massive amount of ...
Nature

Cache Performance and Memory Hierarchy Optimization

The dynamic interplay between processor speed and memory access times has rendered cache performance a critical determinant of computing efficiency. As modern systems increasingly rely on hierarchical ...
Semiconductor Engineering

A Primer On Last-Level Cache Memory For SoC Designs

System-on-chip (SoC) architects have a new memory technology, last level cache (LLC), to help overcome the design obstacles of bandwidth, latency and power consumption in megachips for advanced driver ...